-- Student name: Uyen Nguyen, Joseph Hamann
-- Student ID number: 24701971, 37563702



library IEEE;
use IEEE.std_logic_1164.all;

entity lab2 is
   port(
          clk     : in  STD_LOGIC;
          reset_N : in  STD_LOGIC;
          count   : out STD_LOGIC_VECTOR(2 downto 0)
       );

end lab2;

architecture lab2_arch of lab2 is

-- signal declaration

signal temp: STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ntemp: STD_LOGIC_VECTOR(2 downto 0);

begin
 process(clk, reset_N)
    begin

	if reset_N = '0' then  --on active-high reset asynchronously
            temp <= "000";
	elsif (clk='1' and clk'event) then
	    temp(2) <= ((ntemp(2) and ntemp(1) and ntemp(0)) or (ntemp(2) and ntemp(1) and temp(0)) or (ntemp(2) and temp(1) and ntemp(0)) or (temp(2) and temp(1) and temp(0)));
	                         -- C2'C1'C0' + C2'C1C0' + C2C1'C0' + C2C1C0'
	    temp(1) <= (ntemp(1) and temp(0)) or (temp(1) and ntemp(0));
	                         -- C1'C0 + C1C0'
	    temp(0) <= ntemp(0); -- C0`
	end if;

    end process;

    -- concurrent statement
    ntemp <= not(temp);
    count <= temp;
    
end lab2_arch;


